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publication number s25fl004a_00 revision b amendment 3 issue date july 9, 2007 s25fl004a s25fl004a cover sheet data sheet (retired product) this product has been retired and is not recommended for new designs. for new designs, s25fl040a supersedes s25fl004a. please refer to the s25fl040a for specifications and ordering information. availability of this document is retained for reference and historical purposes only.
2 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet (retired product) this page left intentionally blank.
publication number s25fl004a_00 revision b amendment 3 issue date july 9, 2007 this product has been retired and is not recommended for des igns. for new and current designs, s25fl040a supersedes s25fl004a and is the factory-recommended migration path for th is device. please refer to the s25fl040a data sheet for specifications and ordering information. avai lability of this document is retained for reference and historical purposes only. distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 v read and program operations ? memory architecture ? eight sectors with 512 kb each ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? program operations are on a page by page basis ? erase ? 0.5 s typical sector erase time ? 3 s typical bulk erase time ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? jedec standard two-byte electronic signature ? res command one-byte electronic signature for backward compatibility ? process technology ? manufactured on 0.20 m mirrorbit tm process technology ? package option ? industry standard pinouts ? 8-pin so package (208 mils) ? 8-contact wson package (5 x 6 mm) performance characteristics ? speed ? 50 mhz clock rate (maximum) ? power saving standby mode ? standby mode 20 a (max) ? deep power down mode 1.5 a (typical) memory protection features ? memory protection ? w# pin works in conjunction with status register bits to protect specified memory areas ? status register block protection bits (bp2, bp1, bp0) in status register configure parts of memory as read-only software features ? spi bus compatible serial interface s25fl004a 4 megabit cmos 3.0 volt flash memory with 50mhz spi (serial pe ripheral interface) bus data sheet
4 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet general description the s25fl004a is a 3.0 volt (2.7 v to 3.6 v), single- power-supply flash memory device. the device consists of 8 sectors, each with 512 kb memory. the device accepts data written to si (serial input) and outputs data on so (seria l output). the devices are designed to be programmed in-system wi th the standard system 3.0 volt v cc supply. the memory can be programmed 1 to 256 bytes at a time, using the page program command. the device supports sector erase and bulk erase commands. each device requires only a 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally generated and regulated voltages are provided for the program operations. this device does not require a v pp supply.
july 9, 2007 s25fl004a_00_b3 s25fl004a 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. spansion spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 byte or page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 sector erase / bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3 monitoring write operations using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 data protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.7 hold mode (hold#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.2 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.5 write disable (wrdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.6 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.7 write status register (wrsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.8 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.9 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.10 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.11 deep power down (dp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.12 release from deep power down (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10. power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11. initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 17.1 soc008?8-pin plastic small outline 208-mil body width package . . . . . . . . . . . . . . . . . . 31 17.2 une008?uson 8l (5 x 6 mm) no-lead package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet figures figure 2.1 16-pin plastic small outline package (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.2 8l uson (5 x 6 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6.1 bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6.2 spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7.1 hold mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9.1 read data bytes (read) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9.2 read data bytes at higher speed (fast_read) command sequence . . . . . . . . . . . . . . . 16 figure 9.3 read identification (rdid) command sequence a nd data-out sequence . . . . . . . . . . . . . 17 figure 9.4 write enable (wren) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9.5 write disable (wrdi) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9.6 read status register (rdsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9.7 write status register (wrsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9.8 page program (pp) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9.9 sector erase (se) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9.10 bulk erase (be) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9.11 deep power down (dp) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9.12 release from deep power down (res) command se quence . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9.13 release from deep power down and read electronic signature (res) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10.1 power-up timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15.1 ac measurements i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16.1 spi mode 0 (0,0) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16.2 spi mode 0 (0,0) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16.3 hold# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16.4 write protect setup and hold timing during wr sr when srwd=1 . . . . . . . . . . . . . . . . . . 30
july 9, 2007 s25fl004a_00_b3 s25fl004a 7 data sheet tables table 5.1 s25fl004a valid combinations table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7.1 s25fl004a protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8.1 s25fl004a device organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8.2 s25fl004a sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9.1 read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9.2 s25fl004a status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9.3 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9.4 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10.1 power-up timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14.1 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15.1 test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16.1 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 1. block diagram 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) figure 2.2 8l uson (5 x 6 mm) package s ram p s lo g ic array - l array - r rd data path io x d e c c s # s ck s i s o gnd hold# v cc 1 2 3 4 c s # s o w# gnd s i s ck hold# vcc 5 6 7 8 1 2 3 4 5 6 7 8 cs# vcc so hold# sck si gnd w#
july 9, 2007 s25fl004a_00_b3 s25fl004a 9 data sheet 3. input/output descriptions 4. logic symbol signal name i/o description so (signal data output) output transfers data serially out of the device on the falling edge of sck. si (serial data input) input transfers data serially into the devi ce. device latches commands, addresses, and program data on si on the rising edge of sck. sck (serial clock) input provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs# (chip select) input places device in active power mode when driven low. deselects device and places so at high impedance when high. after power-up, device requires a falling edge on cs# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold# (hold) input pauses any serial communication with the device without deselecting it. when driven low, so is at high impedance, and all input at si and sck are ignored. requires that cs# also be driven low. w# (write protect) input protects the memory area specified by status register bits bp2:bp0. when driven low, prevents any program or erase command from altering the data in the protected memory area. v cc input supply voltage gnd input ground c s # s o w# gnd s i s ck hold# v cc
10 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 5. ordering information the ordering part number is formed by a valid combination of the following: notes 1. contact your local sales office for availability. 2. package marking omits leading ?s25? and speed, package, and model number form. 3. a for standard package (non-pb free); f for pb-free package. 5.1 valid combinations table 5.1 lists the valid combinations configurations planned to be supported in volume for this device. s25fl 004 a 0l m a i 00 1 packing type (note 1) 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 00 = no additional ordering options temperature range i = industrial (?40c to + 85c) package materials a = standard f = lead (pb)-free package type m = 8-pin plastic small outline package (soc008) n = 8-contact uson package (une008) speed 0l = 50 mhz device technology a = 0.20 m mirrorbit? process technology density 004 = 4 mbit device family s25fl spansion tm memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 5.1 s25fl004a valid combinations table s25fl004a valid combinations package marking (note 2) base ordering part number speed option package & temperature model number packing type s25fl004a 0l mai, mfi nai, nfi 00 0, 1, 3 (note 1) fl004a + (temp) + (note 3)
july 9, 2007 s25fl004a_00_b3 s25fl004a 11 data sheet 6. spansion spi modes a microcontroller can use either of its two spi mo des to control spansion spi flash memory devices: ? cpol = 0, cpha = 0 (mode 0) ? cpol = 1, cpha = 1 (mode 3) input data is latched in on the rising edge of sck, and output data is available from the falling edge of sck for both modes. when the bus master is in standby mode, sck is as shown in figure 6.2 for each of the two modes: ? sck remains at 0 for (cpol = 0, cpha = 0 mode 0) ? sck remains at 1 for (cpol = 1, cpha = 1 mode 3) figure 6.1 bus master and memory devices on the spi bus note the write protect (w#) and hold (hold#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. figure 6.2 spi modes supported s pi interf a ce with (cpol, cpha) = (0, 0) or (1, 1) b us m as ter c s3 c s 2c s 1 s pi memory device s pi memory device s pi memory device c s # w# hold# c s # w# hold# c s # w# hold# s ck s o s i s ck s o s i s ck s o s i s o s i s ck m s b m s b s ck s ck s i s o cpha cpol 00 11 c s # mode 0 mode 3
12 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 7. device operations all spansion spi devices (s25fl-a) accept an d output data in bytes (8 bits at a time). 7.1 byte or page programming programming data requires two commands: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus da ta. the page program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. programming means that bits can either be left at 0, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 7.2 sector erase / bulk erase the sector erase (se) and bulk erase (be) commands set all the bits in a sector or the entire memory array to 1. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (se) or array-wide (be) level. 7.3 monitoring write operations using the status register the host system can determine when a write status regist er, program, or erase o peration is complete by monitoring the write in progress (wip) bit in the stat us register. the read from status register command provides the state of the wip bit. 7.4 active power and standby power modes the device is enabled and in the active power mode when chip select (cs#) is low. when cs# is high, the device is disabled, but may still be in the active po wer mode until all program, erase, and write status register operations have completed. the device then goes into the standby power mode, and power consumption drops to i sb . the deep power down (dp) command provides additional data protection against inadvertent signals. after writing the dp command, the device ignores any further program or erase commands, and reduces its power consumption to i dp . 7.5 status register the status register contains the st atus and control bits that can be read or set by specific commands ( table 9.2, s25fl004a status register on page 18 ): ? write in progress (wip): indicates whether the device is performi ng a write status register, program or erase operation. ? write enable latch (wel): indicates the status of the internal write enable latch. ? block protect (bp2, bp1, bp0): non-volatile bits that define memory area to be software-protected against program and erase commands. ? status register write disable (srwd): places the device in the hardwa re protected mode when this bit is set to 1 and the w# input is driven low. in this m ode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits.
july 9, 2007 s25fl004a_00_b3 s25fl004a 13 data sheet 7.6 data protection modes spansion spi flash memory devices provi de the following data protection methods: ? the write enable (wren) command: must be written prior to any command that modifies data. the wren command sets the write enable latch (wel ) bit. the wel bit resets (disables writes) on power-up or after the device completes the following commands : ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write status register (wrsr) ? software protected mode (spm): the block protect (bp2, bp1, bp0) bits define the section of the memory array that can be read but not programmed or erased. table 7.1 shows the sizes and address ranges of protected areas that are defi ned by status register bits bp2:bp0. ? hardware protected mode (hpm): the write protect (w#) input and the status register write disable (srwd) bit together provide write protection. ? clock pulse count: the device verifies that all program, er ase, and write status register commands consist of a clock pulse count that is a multiple of eight before executing them. table 7.1 s25fl004a protected area sizes status register block protect bits memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0 0 0 none (0) 00000?7ffff sa7:sa0 0 0 0 1 70000?7ffff (1) sa7 00000?6ffff sa6:sa0 1/8 0 1 0 60000?7ffff (2) sa7:sa6 00000?5ffff sa5:sa0 1/4 0 1 1 40000?7ffff (4) sa7:sa4 00000?3ffff sa3:sa0 1/2 1 0 0 00000?7ffff (8) sa7:sa0 none none all 1 0 1 00000?7ffff (8) sa7:sa0 none none all 1 1 0 00000?7ffff (8) sa7:sa0 none none all 1 1 1 00000?7ffff (8) sa7:sa0 none none all
14 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 7.7 hold mode (hold#) the hold input (hold#) stops any serial communicatio n with the device, but does not terminate any write status register, program or erase operation that is currently in progress. the hold mode starts on the falling edge of hold# if sck is also low (see figure 7.1 on page 14 , standard use). if the falling edge of hold# does not occur while sc k is low, the hold mode begins after the next falling edge of sck (non-standard use). the hold mode ends on the rising edge of hold# signal (s tandard use) if sck is also low. if the rising edge of hold# does not occur while sck is low, the hold mode ends on the next falling edge of clk (non- standard use) see figure 7.1 . the so output is high impedance, and the si and sck in puts are ignored (don?t care) for the duration of the hold mode. cs# must remain low for the entire duration of the hold mode to ensure that the device internal logic remains unchanged. if cs# goes high while the device is in the ho ld mode, the internal logic is reset. to prevent the device from reverting to the hold mode when device communication is resumed, hold# must be held high, followed by driving cs# low. figure 7.1 hold mode operation 8. sector address table table 8.1 shows the size of the memory array, sectors, and pages. the device uses pages to cache the program data before the data is programmed into the memory array. each page or byte can be individually programmed (bits are changed from 1 to 0). the data is erased (bits are changed from 0 to 1) on a sector- or device-wide basis using the se or be commands. table 8.2 shows the starting and ending address for each sector. the complete set of sectors compri ses the memory array of the flash device. s ck hold# hold condition ( s t a nd a rd us e) hold condition (non- s t a nd a rd us e) table 8.1 s25fl004a device organization each device has each sector has each page has 524,288 65,536 256 bytes 2,048 256 ? pages 8??sectors table 8.2 s25fl004a sector address table sector address range sa7 70000h 7ffffh sa6 60000h 6ffffh sa5 50000h 5ffffh sa4 40000h 4ffffh sa3 30000h 3ffffh sa2 20000h 2ffffh sa1 10000h 1ffffh sa0 00000h 0ffffh
july 9, 2007 s25fl004a_00_b3 s25fl004a 15 data sheet 9. command definitions the host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. on the first rising edge of sck a fter cs# is driven low, the device accepts the one-byte command on si (all commands are one byte long), most significant bit first. each successive bit is latched on the rising edge of sck. table 9.4 on page 24 lists the complete set of commands. every command sequence begins with a one-byte comm and code. the command may be followed by address, data, both, or nothing, depending on the comma nd. cs# must be driven high after the last bit of the command sequence has been written. the read data bytes (read), read status regi ster (rdsr), read data bytes at higher speed (fast_read) and read identification (rdid) command sequences are followed by a data output sequence on so. cs# can be driven high after any bit of th e sequence is output to terminate the operation. the page program (pp), sector erase (se), bulk eras e (be), write status regi ster (wrsr), write enable (wren), or write disable (wrdi) commands require that cs# be driven high at a byte boundary, otherwise the command is not executed. since a byte is composed of eight bits, cs# must therefore be driven high when the number of clock pulses after cs# is driven low is an exact multiple of eight. the device ignores any attempt to access the memory array during a write status register, program, or erase operation, and continue s the operation uninterrupted. 9.1 read data bytes (read) the read data bytes (read) command reads data from the memory array at the frequency (f sck ) presented at the sck input, with a maximum speed of 33 mhz. the host system must first select the device by driving cs# low. the read command is then written to si, followed by a 3-byte address (a23-a0). each bit is latched on the rising edge of sck. the memory array dat a, at that address, are out put serially on so at a frequency f sck , on the falling edge of sck. figure 9.1 and table 9.4 detail the read command sequence. the firs t byte specified can be at any location. the device automatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single read command. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. the read command is terminated by driving cs# high at any time during data output. the device rejects any read command issued while it is executing a progr am, erase, or write status register operation, and continues the operation uninterrupted. figure 9.1 read data bytes (read) command sequence comm a nd 24-bit addre ss hi-z m s b m s b d a t a o u t 1 d a t a o u t 2 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 3 0 29 2 8 10 9 8 7 6 5 4 3 2 1 7 6 5 2 3 22 21 4 3 2 1 0 3 2 10 7 s o s i s ck c s # mode 3 mode 0
16 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 9.2 read data bytes at higher speed (fast_read) the fast_read command reads data from the memory array at the frequency (f sck ) presented at the sck input, with a maximum speed of 50 mhz. the host system must first select the device by driving cs# low. the fast_read command is then written to si, followed by a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. the memory arra y data, at that address, are output serially on so at a frequency f sck , on the falling edge of sck. the fast_read command sequence is shown in figure 9.2 and table 9.4 . the first byte specified can be at any location. the device automatica lly increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single fast_read command. when the highest address is reached, the ad dress counter reverts to 00000h, allowing the read sequence to continue indefinitely. the fast_read command is terminated by driving cs# high at any time during data output. the device rejects any fast_read command issued while it is ex ecuting a program, erase, or write status register operation, and continues the operation uninterrupted. figure 9.2 read data bytes at higher speed (fast_read) command sequence 9.3 read identification (rdid) the read identification (rdid) comm and outputs the one-byte manufacturer identificat ion, followed by the two-byte device id entification, to the host system. jedec assigns the manufacturer identification byte; for spansion devices it is 01h. the device manufacturer assigns the device identification: the first byte prov ides the memory type; the second byte indicates the memory capacity. see table 9.1 or table 9.4 for device id data. the host system must first select the device by drivin g cs# low. the rdid command is then written to si, and each bit is latched on the rising edge of sck. t he 24-bit device identification data is output from the memory array on so at a frequency f sck , on the falling edge of sck. the rdid command sequence is shown in figure 9.3 and table 9.4 . driving cs# high after the device identification data has been read at least once terminates the read_id command. driving cs# high at any time during data output also terminat es the rdid operation. the device rejects any rdid command issued while it is ex ecuting a program, erase, or write status register operation, and continues the operation uninterrupted. c s # s ck s i s o comm a nd 24-bit addre ss d u mmy byte hi-z data out 1 data out 2 m s b m s b 01 2 3 4 56 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 2 3 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7 mode 3 mode 0
july 9, 2007 s25fl004a_00_b3 s25fl004a 17 data sheet figure 9.3 read identification (rdid) comma nd sequence and data-out sequence 9.4 write enable (wren) the write enable (wren) command (see figure 9.4 ) sets the write enable latch (wel) bit to a 1, which enables the device to accept a write status register , program, or erase command . the wel bit must be set prior to every page program (pp), erase (se or be) and write stat us register (wrsr) command. the host system must first drive cs# low, writ e the wren command, and then drive cs# high. figure 9.4 write enable (wren) command sequence table 9.1 read identification (rdi d) data-out sequence manufacturer identification device identification memory type memory capacity 01h 02h 12h 0 1 2 456 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 command msb manufacturer identification device identification hi-z 0 1 2 3 13 14 15 cs# sck si so 3 mode 3 mode 0 c s # s ck s i s o hi-z comm a nd 01 2 3 45 67 mode 3 mode 0
18 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 9.5 write disable (wrdi) the write disable (wrdi) command (see figure 9.5 ) resets the write enable latch (wel) bit to a 0, which disables the device from accepting a write status register, program, or erase command. the host system must first drive cs# low, write the wr di command, and then drive cs# high. any of following conditions resets the wel bit: ? power-up ? write disable (wrdi) command completion ? write status register (wrsr) command completion ? page program (pp) command completion ? sector erase (se) command completion ? bulk erase (be) command completion figure 9.5 write disable (wrdi) command sequence 9.6 read status register (rdsr) the read status register (rds r) command outputs the state of the status register bits. table 9.2 shows the status register bits and their functions. the rdsr command may be written at any time, even wh ile a program, erase, or write status register operation is in progress. the host system should check the write in progress (wip) bit before sending a new command to the device if an operation is already in progress. figure 9.6 shows the rdsr command sequence, which also shows that it is possible to read the status register continuously until cs# is driven high. 0 1 2 3 4 5 6 7 comm a nd c s # hi-z s ck s i s o mode 3 mode 0 table 9.2 s25fl004a status register bit status register bit bit function description 7 srwd status register write disable 1 = protects when w# is low 0 = no protection, even when w# is low 6 ? ? not used 5 ? ? not used 4bp2 block protect 000?111 = protects upper half of address range in 5 sizes. see table 7.1 on page 13 . 3bp1 2bp0 1 wel write enable latch 1 = device accepts write status register, program, or erase commands 0 = ignores write status register, program, or erase commands 0 wip write in progress 1 = device busy. a write status register, program, or erase operation is in progress 0 = ready. device is in standby mode and can accept commands.
july 9, 2007 s25fl004a_00_b3 s25fl004a 19 data sheet figure 9.6 read status register ( rdsr) command sequence the following describes the status and co ntrol bits of the status register. write in progress (wip) bit: indicates whether the device is busy performing a write status register, program, or erase operation. this bit is read-only, and is controlled internally by the device. if wip is 1, one of these operations is in progress; if wip is 0, no such operation is in progress. write enable latch (wel) bit: determines whether the device will accept and execute a write status register, program, or erase command. when set to 1, the device accepts these commands; when set to 0, the device rejects the commands. this bit is set to 1 by writing the wren command, and set to 0 by the wrdi command, and is also automatically reset to 0 after the completion of a write status register, program, or erase operation. wel cannot be directly set by the wrsr command. block protect (bp2, bp1, bp0) bits: define the portion of the memory area that will be protected against any changes to the stored data. the write status register (wrsr) command controls these bits, which are non-volatile. when one or more of these bits is set to 1, the corresponding memory area (see table 7.1 on page 13 ) is protected against page program (pp) and se ctor erase (se) command s. if the hardware protected mode is enabled, bp2:bp0 cannot be changed. the bulk erase ( be) command is executed only if all block protect (bp2, bp1, bp0) bits are 0. status register writ e disable (srwd) bit: provides data protection when used together with the write protect (w#) signal. when srwd is set to 1 and w# is driven low, the device ente rs the hardware protected mode. the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the device ignores any write status register (wrsr) command. 9.7 write status register (wrsr) the write status register (wrsr) command changes the bits in the status register. a write enable (wren) command, which itself sets the write enable latch (wel) in the status register, is required prior to writing the wrsr command. table 9.2, s25fl004a status register on page 18 shows the status register bits and their functions. the host system must drive cs# low, write the wrsr command, and the appropriate data byte on si ( figure 9.7 ). the wrsr command cannot change the state of the write enable latch (bit 1). the wren command must be used for that purpose. bit 0 is a st atus bit controlled internally by the flash device. bits 6 and 5 are always read as 0 and have no user significance. the wrsr command also controls the value of the stat us register write disable (srwd) bit. the srwd bit and w# together place the device in the hardware protected mode (hpm). the device ignores all wrsr commands once it enters the hardware protected mode (hpm). table 9.3 on page 20 shows that w# must be driven low and the srwd bit must be 1 for this to occur. comm a nd hi-z m s b m s b s t a t us regi s ter o u t s t a t us regi s ter o u t 0 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 s o s i s ck c s # mode 3 mode 0
20 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet figure 9.7 write status register (wrsr) command sequence note as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 7.1 on page 13 . table 9.3 shows that neither w# or srwd bit by themselves can enable hpm. the device can enter hpm either by setting the srwd bit after driving w# low, or by driving w# low after setting the srwd bit. however, the device disables hpm only when w# is driven high. note that hpm only protects against changes to the status register. since bp2 :bp0 cannot be changed in hpm, the size of the protected area of the memory array cannot be changed. note that hpm provides no protection to the memory array area outside that specified by bp2:bp0 (software protected mode, or spm). if w# is permanently tied high, hpm can never be acti vated, and only the spm (bp2:bp0 bits of the status register) can be used. 9.8 page program (pp) the page program (pp) command changes specified bytes in the memory array (from 1 to 0 only). a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the pp command, three address bytes, and at least one data byte on si. cs# must be driven low for the enti re duration of the pp sequence. the command sequence is shown in figure 9.8 on page 21 and table 9.4 on page 24 . the device programs only the last 256 data bytes sent to the device. if the number of data bytes exceeds this limit, the bytes sent before the last 256 bytes are disca rded, and the device begins programming the last 256 bytes sent at the starting address of the specified page. this may result in data being programmed into different addresses within the same page than expected. if fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses. the host system must drive cs# high after the device has latc hed the 8th bit of the data byte, otherwise the device does not execute the pp comma nd. the pp operation begins as soon as cs# is driven high. the device internally controls the timing of th e operation, which requires a period of t pp . the status register may be read to check the value of the write in progress (w ip) bit while the pp operation is in progress. the wip bit is 1 during the pp operation, and is 0 when the oper ation is completed. the device internally resets the write enable latch to 0 before the operation co mpletes (the exact timing is not specified). the device does not execute a page pr ogram (pp) command that specifies a page that is protected by the block protect bits (bp2:bp0) (see table 7.1 on page 13 ). table 9.3 protection modes w# signal srwd bit mode write protection of the status register protected area (see note) unprotected area (see note) 11 software protected (spm) status register is writable (if the wren command has set the wel bit). the values in the srwd, bp2, bp1 and bp0 bits can be changed. protected against program and erase commands ready to accept page program and sector erase commands 10 00 01 hardware protected (hpm) status register is hardware write protected. the values in the srwd, bp2, bp1 and bp0 bits cannot be changed. protected against program and erase commands ready to accept page program and sector erase commands hi-z m s b comm a nd s t a t us regi s ter in c s # s ck s i s o 0 12 3 4 5 6 7 7654 3 210 8 9 10 11 12 1 3 14 15 mode 0 mode 3
july 9, 2007 s25fl004a_00_b3 s25fl004a 21 data sheet figure 9.8 page program (pp) command sequence 9.9 sector erase (se) the sector erase (se) command sets all bits at all addre sses within a specified sector to a logic 1. a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the se command plus three address bytes on si. any address within th e sector (see table 7.1 on page 13 ) is a valid address for the se command. cs# must be driven low for the entire duration of the se sequence. the command sequence is shown in figure 9.9 and table 9.4 on page 24 . the host system must drive cs# high after the device has latc hed the 8th bit of the se command, otherwise the device does not execute the co mmand. the se operation begins as s oon as cs# is driven high. the device internally controls the timing of th e operation, which requires a period of t se . the status register may be read to check the value of the write in progress (w ip) bit while the se operation is in progress. the wip bit is 1 during the se operation, and is 0 when the oper ation is completed. the device internally resets the write enable latch to 0 before the operation co mpletes (the exact timing is not specified). the device does not execute an se command that specifie s a sector that is protec ted by the block protect bits (bp2:bp0) (see table 7.1 on page 13 ). figure 9.9 sector erase (se) command sequence 0 3 4 33 3 2 3 1 3 0 29 2 8 10 9 8 7 6 5 4 3 2 1 3 5 3 6 3 7 38 3 9 46 45 44 4 3 42 41 40 47 4 8 49 50 51 52 5 3 54 55 207 3 2072 2076 2075 2074 2079 207 8 2077 2 3 22 21 3 21 07 6 5 4 3 2 1 0 d a t a byte 1 24-bit addre ss comm a nd d a t a byte 2 d a t a byte 3 d a t a byte 256 m s b m s b m s b m s b m s b s ck s i s ck s i 7 65 4 3 2 1 0 76 54 3 21 0 7 6 5 4 3 210 c s # c s # mode 0 mode 3 c s # s ck s i s o m s b comm a nd 24- b it addre ss 01 2 3 45 67 8 910 2 8 29 3 0 3 1 2 3 22 21 3 2 1 0 hi-z mode 0 mode 3
22 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 9.10 bulk erase (be) the bulk erase (be) command sets all the bits within the entire memory array to logic 1s. a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the be command on si . cs# must be driven low for the entire duration of the be sequence. the command sequence is shown in figure 9.10 and table 9.4 on page 24 . the host system must drive cs# high after the device has latched the 8th bit of the ce command, otherwise the device does not execute the co mmand. the be operation begins as s oon as cs# is driven high. the device internally controls the timing of th e operation, which requires a period of t be . the status register may be read to check the value of the write in progress (w ip) bit while the be operation is in progress. the wip bit is 1 during the be operation, and is 0 when the oper ation is completed. the device internally resets the write enable latch to 0 before the operation co mpletes (the exact timing is not specified). the device only executes a be command if al l block protect bits (bp2:bp0) are 0 (see table 7.1 on page 13 ). otherwise, the device ignores the command. figure 9.10 bulk erase (be) command sequence 9.11 deep power down (dp) the deep power down (dp) command provides the lo west power consumption m ode of the device. it is intended for periods when the device is not in active use, and ignores all commands except for the release from deep power down (res) command. the dp mode therefore provides the maximum data protection against unintended write operations. the standard standby mode, which th e device goes into automatically when cs# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. the host system must drive cs# low, and then write th e dp command on si. cs# must be driven low for the entire duration of the dp sequence. the command sequence is shown in figure 9.11 on page 23 and table 9.4 on page 24 . the host system must drive cs# high after the device has latched the 8th bit of the dp command, otherwise the device does not execute the command. after a delay of t dp, the device enters the dp mode and current reduces from i sb to i dp (see table 14.1 on page 26 ). once the device has entered the dp mode, all commands are ignored except the res command (which releases the device from the dp mode). the res comm and also provides the electronic signature of the device to be output on so, if desired (see sections 9.12 and 9.12.1) . dp mode automatically terminates when power is remov ed, and the device always powers up in the standard standby mode. the device rejects any dp command issued while it is executing a program, erase, or write status register operation, and c ontinues the operation uninterrupted. 01 2 4 56 7 comm a nd c s # s ck s i 3 s o hi-z mode 0 mode 3
july 9, 2007 s25fl004a_00_b3 s25fl004a 23 data sheet figure 9.11 deep power down (dp) command sequence 9.12 release from deep power down (res) the device requires the release from deep power down (res) command to exit the deep power down mode. when the device is in the deep power do wn mode, all commands except res are ignored. the host system must drive cs# low and write the res command to si. cs# must be driven low for the entire duration of the sequence. the command sequence is shown in figure 9.12 and table 9.4 on page 24 . the host system must drive cs# high t res(max) after the 8-bit res command byte. the device transitions from dp mode to the standby mode after a delay of t res (see table 16.1 on page 28 ). in the standby mode, the device can execute any read or write command. figure 9.12 release from deep power down (res) command sequence c s # s ck s i s o s t a nd b y mode deep power-down mode comm a nd 0 1 2 3 4567 t dp hi-z mode 0 mode 3 c s # s ck s i s o 0 1 2 3 4 5 6 7 comm a nd deep power-down mode t re s s t a nd b y mode mode 0 hi-z mode 3
24 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 9.12.1 release from deep power down and read electroni c signature (res) the device features an 8-bit el ectronic signature, which can be read using the res command. see figure 9.13 on page 24 and table 9.4 on page 24 for the command sequence and signature value. the electronic signature is not to be confused with the i dentification data obtained us ing the rdid command. the device offers the electronic si gnature so that it can be used with prev ious devices that offered it; however, the electronic signature should not be used for new designs, which should read the rdid data instead. after the host system drives cs# low, it must write the res command follo wed by 3 dummy bytes to si (each bit is latched on si during the rising edge of sck). the electronic signature is then output on so; each bit is shifted out on the falling edge of sc k. the res operation is terminated by driving cs# high after the electronic signature is read at least once. additional clock cycles on sck with cs# low cause the device to output the electronic si gnature repeatedly. when cs# is driven high, the device transitions from dp mode to the standby mode after a delay of t res , as previously described. the res command always provides access to the electronic signature of the device and can be applied even if dp mode has not been entered. any res command issued while an erase, program, or wrsr operation is in progress not executed, and the operation continues uninterrupted. figure 9.13 release from deep power down and read electronic signature (res) command sequence notes 1. the s25fl004a has a manufacturer id of 01h, and a device id co nsisting of the memory type (02h) and the memory capacity (12h) . c s # s ck s i s o 3 d u mmy byte s hi-z m s b deep power-down mode s t a nd b y mode 0 1 2 3 4567 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 electronic id o u t comm a nd t re s 2 3 22 21 3 2 10 7 65 4 3 2 1 0 m s b table 9.4 command definitions operation command description one-byte command code address bytes dummy byte data bytes read read read data bytes 03h (0000 0011) 3 0 1 to fast_read read data bytes at higher speed 0bh (0000 1011) 3 1 1 to rdid read identification (note 1) 9fh (1001 1111) 0 0 1 to 3 write control wren write enable 06h (0000 0110) 0 0 0 wrdi write disable 04h (0000 0100) 0 0 0 erase se sector erase d8h (1101 1000) 3 0 0 be bulk (chip) erase c7h (1100 0111) 0 0 0 program pp page program 02h (0000 0010) 3 0 1 to 256 status register rdsr read from status register 05h (0000 0101) 0 0 1 to wrsr write to status register 01h (0000 0001) 0 0 1 power saving dp deep power down b9h (1011 1001) 0 0 0 res release from deep power down abh (1010 1011) 0 0 0 release from deep power down and read electronic signature (note 2) abh (1010 1011) 0 3 1 to
july 9, 2007 s25fl004a_00_b3 s25fl004a 25 data sheet 2. the s25fl004a has an electr onic signature id of 12h. 10. power-up and power-down during power-up and power-down, certain conditions mu st be observed. cs# must follow the voltage applied on v cc , and must not be driven low to select the device until v cc reaches the allowable values as follows (see figure 10.1 on page 25 and table 10.1 on page 25 ): ? at power-up, v cc (min) plus a period of t pu ? at power-down, v ss a pull-up resistor on chip select (cs#) typically meets proper power-up and power-down requirements. no write status register, progr am, or erase command should be sent to the device until v cc rises to the v cc min, plus a delay of t pu . at power-up, the device is in standby mode (not deep power down mode) and the wel bit is reset (0). each device in the host system should have the v cc rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the or der of 0.1 f), as a precaution to stabilizing the v cc feed. when v cc drops from the operating voltage to below the minimum v cc threshold at power-down, all operations are disabled and the device does not res pond to any commands. note that data corruption may result if a power-down occurs while a write regi ster, program, or erase operation is in progress. figure 10.1 power-up timing diagram 11. initial delivery state the device is delivered with all bits set to 1 (each byte contains ffh) upon initial factory shipment. the status register contains 00h (all status register bits are 0). table 10.1 power-up timing characteristics symbol parameter min max unit v cc(min) v cc (minimum) 2.7 v t pu v cc (min) to device operation 10 ms v cc v cc (max) v cc (min) full device access t pu time
26 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 12. absolute maximum ratings do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. these are stress ratings only and device oper ation at these or any other conditions beyond those indicated in this section and in the operating ranges on page 26 section of this document is not implied. device operation for extended periods at the limits listed in this se ction may affect device reliability. 13. operating ranges note operating ranges define those limits between wh ich functionality of the device is guaranteed. 14. dc characteristics this section summarizes the dc char acteristics of the device. designers should check that the operating conditions in their circuit match the measurement c onditions specified in the test specifications in table 15.1 on page 27 , when relying on the quoted parameters. note typical values are at t a = 25 c and 3.0 v. table 12.1 absolute maximum ratings description rating ambient storage temperature ?65c to +150c voltage with respect to ground: all inputs and i/os ?0.3 v to 4.5 v table 13.1 operating ranges description rating ambient operating temperature (t a ) commerical 0c to +70c industrial ?40c to +85c positive power supply voltage range 2.7 v to 3.6 v table 14.1 dc characteristics (cmos compatible) parameter description test conditions (see note) min typ. max unit v cc supply voltage 2.7 3 3.6 v i cc1 active read current sck = 0.1 v cc /0.9v cc 33 mhz 912ma sck = 0.1 v cc /0.9v cc v cc = 3.0v, 50 mhz 13 ma i cc2 active page program current cs# = v cc 16.5 27 ma i cc3 active wrsr current cs# = v cc 24 ma i cc4 active sector erase current cs# = v cc 24 ma i cc5 active bulk erase current cs# = v cc 24 ma i sb standby current v cc = 3.0 v cs# = v cc 20 50 a i dp deep power down current v cc = 3.0 v cs# = v cc 1.5 5 a i li input leakage current v in = gnd to v cc 1a i lo output leakage current v in = gnd to v cc 1a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?0.1 ma v cc ? 0.2 v
july 9, 2007 s25fl004a_00_b3 s25fl004a 27 data sheet 15. test conditions figure 15.1 ac measurements i/o waveform table 15.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0. 8 v cc 0.2 v cc 0.7 v cc 0. 3 v cc inp u t level s inp u t a nd o u tp u t 0.5 v cc
28 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 16. ac characteristics notes 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v; 10,000 cycles; checkerboard data pattern 2. under worst-case conditions of 90 c; v cc = 2.7v; 100,000 cycles 3. not 100% tested table 16.1 ac characteristics symbol (notes) parameter min typ (notes) max (notes) unit f sck sck clock frequency read command d.c. 33 mhz f sck sck clock frequency for: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 50 mhz t crt clock rise time (slew rate) 0.1 v/ns t cft clock fall time (slew rate) 0.1 v/ns t wh sck high time 9 ns t wl sck low time 9 ns t cs cs# high time 100 ns t css (3) cs# setup time 5 ns t csh (3) cs# hold time 5 ns t hd (3) hold# setup time (relative to sck) 5 ns t cd (3) hold# hold time (relative to sck) 5 ns t hc hold# setup time (relative to sck) 5 ns t ch hold# hold time (relative to sck) 5 ns t v output valid 10 ns t ho output hold time 0 ns t hd:dat data in hold time 5 ns t su:dat data in setup time 5 ns t r input rise time 5ns t f input fall time 5ns t lz (3) hold# to output low z 10 ns t hz (3) hold# to output high z 10 ns t dis (3) output disable time 10 ns t wps (3) write protect setup time 15 ns t wph (3) write protect hold time 15 ns t w write status register time 67 150 ms t dp cs# high to deep power down mode 3 s t res release dp mode 30 s t pp page programming time 1.5 (1) 3 (2) ms t se sector erase time 0.5 (1) 3 (1) sec t be bulk erase time 3 (1) 24 (1) sec
july 9, 2007 s25fl004a_00_b3 s25fl004a 29 data sheet figure 16.1 spi mode 0 (0,0) input timing figure 16.2 spi mode 0 (0,0) output timing figure 16.3 hold# timing c s # s ck s i s o t c s h t c ss t c s h t c ss t crt t cft m s b in l s b in hi-z t s u:dat t hd:dat t c s c s # s ck s o l s b out t wh t wl t di s t v t ho t v t ho t ch t hz t cd t hd t hc t lz c s # s ck s o s i hold#
30 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet figure 16.4 write protect setup and hold timing during wrsr when srwd=1 w# c s # s ck s i s o hi-z t wp s t wph
july 9, 2007 s25fl004a_00_b3 s25fl004a 31 data sheet 17. physical dimensions 17.1 soc008?8-pin plastic small out line 208-mil body width package 3432 \ 16-038.03 \ 10.28.04 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane. . package soc 008 (inches) soc 008 (mm) jedec symbol min max min max a 0.069 0.085 1.753 2.159 a1 0.002 0.0098 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0.356 0.483 b1 0.013 0.018 0.330 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.008 0.152 0.203 d 0.208 bsc 5.283 bsc e 0.315 bsc 8.001 bsc e1 0.208 bsc 5.283 bsc e .050 bsc 1.27 bsc l 0.020 0.030 0.508 0.762 l1 .055 ref 1.40 ref l2 .010 bsc 0.25 bsc n 8 8 0? 8? 0? 8? 1 5? 15? 5? 15? 2 0? 0? 9 c a a1 a2 b e 5 b d e e/2 5 e1/2 4 3 e1 3 seating plane 4 d a 0.10 0.10 a-b 0.20 c a-b c c c md 0.25 0.33 c h see detail b b1 c1 7 (b) c with plating base metal section a-a 2 0.07 r min. 1 l1 c l2 a a l gauge plane seating plane h detail b q q q
32 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet 17.2 une008?uson 8l (5 x 6 mm) no-lead package 3448\ 16-038.28 \ 04.15.05 notes: 1. dimensioning and tolerancing conforms to asme y14.5m-1994. 2. all dimensions are in millimeters, 0 is in degrees. 3. n is the total number of terminals. 4. dimension b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. nd refers tot he number of terminals on d side. 6. maximum package warpage is 0.05 mm. 7. maximum allowable burrs is 0.076 mm in all directions. 8. pin #1 id on top will be laser marked. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. quad flat no lead packages (une) - plastic dimensions symbol min nom max note e 1.27 bsc n 8 3 nd 4 5 l 0.55 0.60 0.65 b 0.35 0.40 0.45 4 d2 3.90 4.00 4.10 e2 3.30 3.40 3.50 d 5.00 bsc e 6.00 bsc a 0.45 0.50 0.55 a1 0.00 0.02 0.05 k 0.20 max. 0 --- 12 2
july 9, 2007 s25fl004a_00_b3 s25fl004a 33 data sheet 18. revision history section description revision a (march 1, 2005) global initial release. revision a1 (march 28, 2005) global updated table 7.removed commercial temperature range. changed wson package nomenclature to uson package; updated uson package dimensions. added tray option for packing type. revision a2 (august 10, 2005) global changed document status to preliminary. 8-contact uson package not pb-free. changed power saving standby mode to 20 a (typical); deep power down mode to 1.5 a; typical sector erase time to 0.5 s; typical bulk erase time to 3 s. ordering information changes in information and notations in ordering information table. dc characteristics information changes in the dc characteristics table. ac characteristics information changes in the ac characteristics table. revision a3 (may 19, 2006) global removed preliminary document status. revision a4 (june 29, 2006) dc characteristics added typical specificat ion and changed maximum specification for i cc2 . revision b0 (august 31, 2006) global rewrote entire document for better flow and clarity. no specifications were changed. revision b1 (january 23, 2007) global added migration text to cover sheet and first page document. revision b2 (july 2, 2007) global added a sentence to byte or page programming. revision b3 (july 9, 2007) global modified migration text to cover sheet and first page document. this product is now retired.
34 s25fl004a s25fl004a_00_b3 july 9, 2007 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2005?2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries . other names used are for informational purposes only and may be trademarks of their respective owners.

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